1. Field of the Invention
The present invention relates to a semiconductor device such as a large scale integrated circuit (LSI) and a method of manufacturing the same.
2. Description of the Prior Art
Conventionally, a semiconductor device includes a plurality of pads as an electrode and the pads are formed together with power supply/ground wiring lines and wiring lines for supplying associated control signals to a memory cell unit and a control circuit in the same metal wiring layer. The memory cell unit and the control circuit are formed in the center of the semiconductor device and on the other hand, the pads are formed at the periphery thereof. Those pads are made in contact with, for example, the ends of probe tips on a probe card when a wafer-probe test is performed. This enables the semiconductor device to be connected to a test circuit and then, the electrical characteristics of the semiconductor device are measured to inspect the device. Furthermore, the pads thus configured physically and electrically are connected to, for example, lead terminals of a lead frame via bonding wires in the assembly process of the semiconductor device.
Recently, as a semiconductor device has been fabricated at high integration density, miniaturization of elements of a semiconductor device has been enhanced. However, the relevant techniques associated with probe tips on a probe card or wire bonding cause a limitation in the actions to enhance the miniaturization, making it difficult to reduce the area of a pad itself. In more detail, even when elements of a semiconductor device are formed small in size and fabricated in high density to reduce the area of individual elements, ratio of the area occupied by pads to the area of the semiconductor device tends to increase. For this reason, allocating space for a plurality of pads formed in the same metal wiring layer as that provided for power supply/ground wiring lines and wiring lines for supplying associated signals to a memory cell unit and a control circuit contributes to one of primary causes to prevent reduction of dimensions of an entire semiconductor device. Accordingly, it has been found as a problem associated with the conventional techniques that the number of chips on a wafer cannot be made to largely increase.
In addition, the number of types of semiconductor device tends to increase in response to diversification in the applications where semiconductor devices are employed. This results in a wider variety of pad layouts. For this reason, there arises the need to newly prepare a probe card and then modify a specification for designing a lead frame so as to correspond to each of various layouts of pads. This increases the cost of, for example, manufacturing a probe card and designing a lead frame, resulting in current increase in cost of manufacturing a semiconductor device.
The present invention has been conceived in consideration of the above-described problems and is directed to a semiconductor device capable of reducing its size and increasing the number of chips on a wafer, and further a method of manufacturing the same.